`timescale 1ns/1ns
module black_ctrl(
                input   wire            resetb,
                input   wire            sclk,
                
                input   wire            time_125ms_sync,
                input   wire            init_mode,
                input   wire            input_active,
                input   wire            local_test_en,
                
                input   wire            black_mark,                  
                input   wire [7:0]      state, 
                input   wire [7:0]      no_vs_set,
                
                output  reg             black
                );    

parameter       INIT_STATE      =       5'h01;
parameter       DELAY_1         =       5'h02;
parameter       DISPLAY_STATE   =       5'h04;
parameter       BLACK_STATE     =       5'h08;
parameter       DELAY_2         =       5'h10;                

reg     [4:0]   display_state;
reg     [1:0]   delay_count;
reg             delay_end;

always@(posedge sclk or negedge resetb)
        if(resetb==1'b0)
                display_state<=INIT_STATE;
        else if(init_mode==1)
                display_state<=INIT_STATE;
        else begin
                case(display_state)   
                        INIT_STATE:     if(init_mode==0)
                                                display_state<=DELAY_1; 
                                                
                        DELAY_1:        if(delay_end==1'b1)  begin
                                                if(input_active=='b0 && no_vs_set[3:0]==4'h0) 
                                                        display_state<=BLACK_STATE;
                                                else 
                                                        display_state<=DISPLAY_STATE;  
                                                end        
                                                                                                                      
                        DISPLAY_STATE:  if(input_active=='b0 && no_vs_set[3:0]==4'h0 && local_test_en==1'b0)        
                                                display_state<=BLACK_STATE;
                                                
                        BLACK_STATE:    if(input_active==1'b1)
                                                display_state<=DELAY_2;
                                        else if(local_test_en==1'b1)        
                                                display_state<=DISPLAY_STATE;
                                                
                        DELAY_2:        if(delay_end==1'b1)
                                                display_state<=DISPLAY_STATE;
                                                
                        default:        display_state<=INIT_STATE;        
                        endcase        
                end  
                
always@(posedge sclk or negedge resetb)
        if(resetb==1'b0)
                delay_count<=2'h0;
        else if(display_state!=DELAY_1 && display_state!=DELAY_2)
                delay_count<=2'h0;
        else if(time_125ms_sync==1'b1)
                delay_count<=delay_count+1;
                
always@(posedge sclk or negedge resetb)
        if(resetb==1'b0)
                delay_end<=1'b0;
        else if(display_state!=DELAY_1 && display_state!=DELAY_2)                                        
                delay_end<=1'b0;
        else if(delay_count[1]==1'b1)
                delay_end<=1;

always@(posedge sclk or negedge resetb)
        if(resetb==1'b0)
                black<=1;
        else if(display_state!=DISPLAY_STATE || state[3] || black_mark)
                black<=1;
        else
                black<=0;
                
endmodule
                                